A critical problem for advanced stacked memory circuitry, and particularly DRAM circuitry, is storage node to storage node shorts. The storage node is a conductor, typically comprised of conductively doped polysilicon. Due to the topography that is intentionally created in forming a stacked capacitor for maximizing cell capacitance, topographical canyons are created which can fill with storage node polysilicon. Even with extensive over-etching of the polysilicon, a residual polysilicon filament (stringer) can remain in such canyons which electrically connects (shorts) adjacent storage nodes. The problem will be more easily understood with reference to FIGS. 1-5.
FIG. 1 is a top plan view illustrating a semiconductor wafer fragment 10 comprised in part of two pairs of mirror image word lines 12, 14. Word line pair 12 includes individual word lines 16, 18, while word line pair 14 includes individual word lines 20, 22. FIGS. 2, 3 and 4 depict the various sections through lines 2--2, 3--3 and 4--4 respectively, in FIG. 1. Wafer fragment 10 comprises active regions 38. As well, outlines 40 for capacitors to be formed which overlap adjacent pairs of word lines are illustrated. Outlines 42 are shown for subsequent bit line contacts. Bit lines are not shown for sake of clarity with respect to the capacitor constructions. Also illustrated are buried contact outlines 28. FIGS. 2, 3 and 4 illustrate storage polysilicon 30 deposition, as well as patterning of a photoresist layer 32 used to define lower capacitor storage node plates.
The large vertical topography created by forming the stacked storage polysilicon node over the word lines is clearly evident in the FIG. 2 cross-section. FIGS. 3 and 4 show regions of the device at the same point in the process, i.e. just prior to lower capacitor plate polysilicon etch. These regions are located between the storage nodes, and are locations where all storage node polysilicon needs to be removed during lower capacitor plate/storage node etch. However, it is apparent from FIGS. 3 and 4 that the storage node polysilicon is bridged in the 3--3 and 4--4 regions forming deep filled polysilicon trenches 33 and 35 respectively, that are difficult to remove. The result is that it is difficult to ensure that after the storage node etch there is not any polysilicon filament remaining in these deep canyons that electrically bridges adjacent storage nodes.
The problem created by failure to remove all bridging polysilicon can be seen by referring to FIGS. 1 and 5. FIG. 5 is a view corresponding to the FIG. 3 section taken subsequent to the polysilicon etch. As illustrated, a stringer region 34 remains after removal of polysilicon layer 30. This creates multiple stringer shorts between storage nodes, with one such short being shown by dashed lines 34 in FIG. 1.
It would be desirable to overcome these and other drawbacks associated with the prior art.